Submitted by Sebastian on Tue, 03/07/2017 - 16:25
We are very proud to announce that apertus° has been accepted as a new mentoring organization for this year’s Google Summer of Code (GSoC). As only a small number of new organizations are allowed to join each year and the majority already in the program have been participating for many years, this is especially exciting. For anyone not familiar, GSoC is a program where students are paid to contribute to selected open source projects between June and August.
Project Overview apertus° GSoC Profile apertus° Idea List apertus° GSoC Mailinglist
FPGA Hackers wanted
Field Programmable Gate Arrays (FPGAs) and their embedded systems are central to the AXIOM camera's design so these will feature in many of our GSoC projects. For anyone not already familiar, FPGAs are hardware (in general a chip) which contains a huge number of predefined resources, so called Gates - which are actaully lookup tables (LUTs) nowadays - and flip-flops (FFs), which can be reconfigured by uploading a specific bitstream (the software) into the volatile configuration memory. As these logic elements can be connected to each other in many possible configurations, the firmware needs to be carefully designed to ensure it works exactly as intended. This is where the hardware description language (HDL) comes in. HDL lets developers describe the functional aspects of the design without the need to bother about the low-level electrical details. FPGAs are able to process huge amounts of data in a highly optimized, pipelined and parallelized way, which makes them perfect for real-time data crunching like processing high speed high resolution raw video. This year, in collaboration with other GSoC projects TimVideos.us and FOSSi, we're looking for people who want to get their hands dirty with FPGAs :)
Projects excerpt:
FPGA real time Sobel Filter
VHDL logic to calculate/detect real time contrast/gradients (sobel) values from an image. This can be utilized for implementing autofocus or focus peaking.
4K HDMI output HDL gear work Logic / IP Core
The AXIOM Beta will soon feature a plugin module with a Xilinx Artix FPGA and gigabit transceivers to act as gear work for the ZYNQ 4K/UHD HDMI output.
These are just a couple of project ideas from the list so feel free to browse and get in touch - we’re happy to share our ideas and are especially interested in hearing your own.
Timeline
| February 27 - March 20 | Potential student participants discuss application ideas with mentoring organizations. |
| March 20 16:00 UTC | Student application period opens |
| April 3 16:00 UTC | Student application deadline |
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