AXIOM Alpha Milestone Reached



It's about time

Today is a major milestone on our path to having a working Axiom Alpha prototype! After months of designing, routing, checking, double-checking and then revising our designs, we have now placed an order for the final version of the printed circuit boards (PCBs) we will be implementing in our prototype.

The Image Sensor Front End (SFE)


PCB Top Side.

PCB Bottom Side.

This 4 layer PCB will act as the bridge between our image sensor: the CMV12000 (providing a native resolution of 4096x3072 pixels - more details are available on the Axiom Minisite) and our prototyping platform - the Zedboard. Inside the FPGA, all image data taken from the sensor will be read into memory, preprocessed and then output as a video stream over HDMI.

OSH Park

Our prints are being manufactured by the kind folks at Open Source Hardware Park, which is a community-based printed circuit board (PCB) ordering service. Their business model revolves around receiving designs from a range of clients, placing them alongside one another on a combined board and then ordering the said board from a fabrication lab. This allows their customers to purchase low volume prints at very reasonable prices. The downside to this however, is that customers may have to wait for batches to fill up before their design can be sent off to the fab facility, printed and then shipped back to OSH Park. More information can be found on their website, which is also set up to allow members of this thriving community to share open hardware PCB designs quickly and with ease. But of course, our schematics and board layouts are on GitHub as well.

What's next?

With all of this said and done, we must now wait up to 4 weeks for the boards to arrive (since they are grouped into batches and we don't know exactly when one batch will fill to maximum capacity and be sent off to the factory). Once our boards arrive, we will immediately get to work populating and testing the board. Whilst you would normally plan for a second and third hardware revision to get everything into an optimised working state, we don't think there will be too many problems with our initial design. After this, we will proceed to work on the FPGA code, dealing with things like image pre-processing, data and memory management.

Things learned along the way


PMOD Debug V1.0 Bottom.

PMOD Debug V1.0 Top.

In accordance with our mission statement we have promised to share the knowledge gained throughout our development trajectory. This has now lead to our first side-product: A debug PMOD interface for FPGA development featuring 64 LEDS that can easily be interfaced from inside the FPGA (and which we are using to display "state information"). With the FPGA executing all instructions concurrently, you cannot inspect actions in a step-by-step manner and debug FPGA operations like normal code with breakpoints. As such, this LED matrix is a convenient way to visualise all the processes performed inside the FPGA with your code. We are still thinking about offering these modules fully assembled in our webshop. Let us know if you would be interested in something like this so that we may allocate our limited resources to making it happen.


Cover Photo under CC by Jeff Turner
Project: 

10 Comments

4 years ago
tiagoh

nice step ! keep moving forward :)

4 years ago
Engineer

By my calculations that's about 1.5GBps, or about the speed of 3-4 SSDs working in parallel.

This is what it would take to store 10-bit-per-pixel RAW output at 4k and 150fps. (Which is what the goal is for the final camera, as i understand it.)

4 years ago
Francis

1. custom board with LVDS interconnection. will solve the speed but the price would be high because of the low volume. the integration should be simple (most highspeed camera's use this approach)
2. board with 2x ssd M.2 format connection will be pci-e. solves speed and price tag but would need MAYBE a SATA controller.
3. ssd 2.5" with pci-e connection. solves speed, price is tag still open(i hope in the area of 1000$ for a 512 GB ssd), requires pci-e 3.0 4x at least.
---
the target should be not to use sata and go direct with sata express (pci-e with nvm) but i'm not sure how hard the fpga implementation is. my knowledge about vhdl and verilog is limited.

4 years ago
KurtF

Congratulations to everyone. Fantastic milestone on the way to Open Source Digital Cinema. I'm looking forward to hearing further progress on the FPGA firmware, and eventually some actual footage.

Well done.

4 years ago
Jason

Will the final Axiom camera have Genlock? I am thinking it would be great for stereoscopic 3D video recording.

4 years ago
Sebastian

I can neither deny nor confirm the existance of Genlock in the Axiom camera...
Though the future existance is slightly more likely than finding extra terrestrial life in the next year... :)

4 years ago
derkiki

I would like to complement you on the site and the great, well-written updates. Your project is more than a camera, it's a great example for collaboration and open hard- and software. All the best in these competitive times!

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