PMOD Debug Board


A debug PMOD interface for FPGA development (like for the Zedboard) featuring 64 LEDS that can conveniently be interfaced from inside the FPGA. With the FPGA executing all instructions concurrently, you cannot inspect actions in a step-by-step manner and debug FPGA operations like normal code with breakpoints. As such, this LED matrix is a convenient way to visualize all the processes performed inside the FPGA with your VHDL code. The LEDs are multiplexed (4 blocks: LO, RO, LU, RU with 16 LEDs each) with a 4:16 decoder.

PCB Top Side.
PCB Bottom Side.

Size: 57.30 x 15.52 mm

Source Files

Download: PCB Board Layout Files

License: CERN Open Hardware License


Order (unpopulated PCB): OSH Park PCB Service

Order populated PCB: Contact us

Example VHDL Code

--  pmod_debug.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--  Copyright (C) 2013 H.Poetzl
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity pmod_debug is
    port (
	clk	: in std_logic;				-- base clock
	value	: in std_logic_vector(63 downto 0);	-- '1' on '0' off
	update	: in std_logic;				-- load
	jxm	: out std_logic_vector(3 downto 0);	-- mask '0' = on
	jxa	: out std_logic_vector(3 downto 0)	-- address (inv)

end entity pmod_debug;

architecture RTL of pmod_debug is

    pmod_vis: process(clk, value, update)
	variable vis_addr : natural range 0 to 15 := 15;
	variable vis_cnt : natural range 0 to 15 := 0;
	variable mem : std_logic_vector(63 downto 0);
	if rising_edge(update) then
	    mem := value;
	end if;

	if rising_edge(clk) then
	    if vis_cnt = 0 then		-- setup address

Constraints file (*.xdc) containing port definitions for port JC and JD

set_property PACKAGE_PIN AB7 [get_ports {pmod_jcm[0]}]
set_property PACKAGE_PIN AB6 [get_ports {pmod_jcm[1]}]
set_property PACKAGE_PIN AA4 [get_ports {pmod_jcm[2]}]
set_property PACKAGE_PIN Y4 [get_ports {pmod_jcm[3]}]

set_property PACKAGE_PIN U4 [get_ports {pmod_jca[0]}]
set_property PACKAGE_PIN T4 [get_ports {pmod_jca[1]}]
set_property PACKAGE_PIN T6 [get_ports {pmod_jca[2]}]
set_property PACKAGE_PIN R6 [get_ports {pmod_jca[3]}]

set_property PACKAGE_PIN V7 [get_ports {pmod_jdm[0]}]
set_property PACKAGE_PIN W7 [get_ports {pmod_jdm[1]}]
set_property PACKAGE_PIN V4 [get_ports {pmod_jdm[2]}]
set_property PACKAGE_PIN V5 [get_ports {pmod_jdm[3]}]

set_property PACKAGE_PIN U5 [get_ports {pmod_jda[0]}]
set_property PACKAGE_PIN U6 [get_ports {pmod_jda[1]}]
set_property PACKAGE_PIN W5 [get_ports {pmod_jda[2]}]
set_property PACKAGE_PIN W6 [get_ports {pmod_jda[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports pmod_*]

Project Type: Hardware Status: Completed
go back up